// +build f303xe

// Peripheral: SYSCFG_Periph  System configuration controller.
// Instances:
//  SYSCFG  mmap.SYSCFG_BASE
// Registers:
//  0x00 32  CFGR1      Configuration register 1.
//  0x04 32  RCR        CCM SRAM protection register.
//  0x08 32  EXTICR[4]  External interrupt configuration registers.
//  0x18 32  CFGR2      Configuration register 2.
//  0x1C 32  RESERVED0  Reserved,                                                          0x1C.
//  0x20 32  RESERVED1  Reserved,                                                          0x20.
//  0x24 32  RESERVED2  Reserved,                                                          0x24.
//  0x28 32  RESERVED4  Reserved,                                                          0x28.
//  0x2C 32  RESERVED5  Reserved,                                                          0x2C.
//  0x30 32  RESERVED6  Reserved,                                                          0x30.
//  0x34 32  RESERVED7  Reserved,                                                          0x34.
//  0x38 32  RESERVED8  Reserved,                                                          0x38.
//  0x3C 32  RESERVED9  Reserved,                                                          0x3C.
//  0x40 32  RESERVED10 Reserved,                                                          0x40.
//  0x44 32  RESERVED11 Reserved,                                                          0x44.
//  0x48 32  CFGR4      Configuration register 4.
//  0x4C 32  RESERVED12 Reserved,                                                          0x4C.
//  0x50 32  RESERVED13 Reserved,                                                          0x50.
// Import:
//  stm32/o/f303xe/mmap
package syscfg

// DO NOT EDIT THIS FILE. GENERATED BY stm32xgen.

const (
	MEM_MODE            CFGR1 = 0x07 << 0  //+ SYSCFG_Memory Remap Config.
	MEM_MODE_0          CFGR1 = 0x01 << 0  //  Bit 0.
	MEM_MODE_1          CFGR1 = 0x02 << 0  //  Bit 1.
	MEM_MODE_2          CFGR1 = 0x04 << 0  //  Bit 2.
	USB_IT_RMP          CFGR1 = 0x01 << 5  //+ USB interrupt remap.
	TIM1_ITR3_RMP       CFGR1 = 0x01 << 6  //+ Timer 1 ITR3 selection.
	DAC1_TRIG1_RMP      CFGR1 = 0x01 << 7  //+ DAC1 Trigger1 remap.
	DMA_RMP             CFGR1 = 0x79 << 8  //+ DMA remap mask.
	ADC24_DMA_RMP       CFGR1 = 0x01 << 8  //  ADC2 and ADC4 DMA remap.
	TIM16_DMA_RMP       CFGR1 = 0x08 << 8  //  Timer 16 DMA remap.
	TIM17_DMA_RMP       CFGR1 = 0x10 << 8  //  Timer 17 DMA remap.
	TIM6DAC1Ch1_DMA_RMP CFGR1 = 0x20 << 8  //  Timer 6 / DAC1 Ch1 DMA remap.
	TIM7DAC1Ch2_DMA_RMP CFGR1 = 0x40 << 8  //  Timer 7 / DAC1 Ch2 DMA remap.
	I2C_PB6_FMP         CFGR1 = 0x01 << 16 //+ I2C PB6 Fast mode plus.
	I2C_PB7_FMP         CFGR1 = 0x01 << 17 //+ I2C PB7 Fast mode plus.
	I2C_PB8_FMP         CFGR1 = 0x01 << 18 //+ I2C PB8 Fast mode plus.
	I2C_PB9_FMP         CFGR1 = 0x01 << 19 //+ I2C PB9 Fast mode plus.
	I2C1_FMP            CFGR1 = 0x01 << 20 //+ I2C1 Fast mode plus.
	I2C2_FMP            CFGR1 = 0x01 << 21 //+ I2C2 Fast mode plus.
	ENCODER_MODE        CFGR1 = 0x03 << 22 //+ Encoder Mode.
	ENCODER_MODE_TIM2   CFGR1 = 0x01 << 22 //  TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively.
	ENCODER_MODE_TIM3   CFGR1 = 0x02 << 22 //  TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively.
	I2C3_FMP            CFGR1 = 0x01 << 24 //+ I2C3 Fast mode plus.
	FPU_IE              CFGR1 = 0x3F << 26 //+ Floating Point Unit Interrupt Enable.
)

const (
	MEM_MODEn       = 0
	USB_IT_RMPn     = 5
	TIM1_ITR3_RMPn  = 6
	DAC1_TRIG1_RMPn = 7
	DMA_RMPn        = 8
	I2C_PB6_FMPn    = 16
	I2C_PB7_FMPn    = 17
	I2C_PB8_FMPn    = 18
	I2C_PB9_FMPn    = 19
	I2C1_FMPn       = 20
	I2C2_FMPn       = 21
	ENCODER_MODEn   = 22
	I2C3_FMPn       = 24
	FPU_IEn         = 26
)

const (
	PAGE0  RCR = 0x01 << 0  //+ ICODE SRAM Write protection page 0.
	PAGE1  RCR = 0x01 << 1  //+ ICODE SRAM Write protection page 1.
	PAGE2  RCR = 0x01 << 2  //+ ICODE SRAM Write protection page 2.
	PAGE3  RCR = 0x01 << 3  //+ ICODE SRAM Write protection page 3.
	PAGE4  RCR = 0x01 << 4  //+ ICODE SRAM Write protection page 4.
	PAGE5  RCR = 0x01 << 5  //+ ICODE SRAM Write protection page 5.
	PAGE6  RCR = 0x01 << 6  //+ ICODE SRAM Write protection page 6.
	PAGE7  RCR = 0x01 << 7  //+ ICODE SRAM Write protection page 7.
	PAGE8  RCR = 0x01 << 8  //+ ICODE SRAM Write protection page 8.
	PAGE9  RCR = 0x01 << 9  //+ ICODE SRAM Write protection page 9.
	PAGE10 RCR = 0x01 << 10 //+ ICODE SRAM Write protection page 10.
	PAGE11 RCR = 0x01 << 11 //+ ICODE SRAM Write protection page 11.
	PAGE12 RCR = 0x01 << 12 //+ ICODE SRAM Write protection page 12.
	PAGE13 RCR = 0x01 << 13 //+ ICODE SRAM Write protection page 13.
	PAGE14 RCR = 0x01 << 14 //+ ICODE SRAM Write protection page 14.
	PAGE15 RCR = 0x01 << 15 //+ ICODE SRAM Write protection page 15.
)

const (
	PAGE0n  = 0
	PAGE1n  = 1
	PAGE2n  = 2
	PAGE3n  = 3
	PAGE4n  = 4
	PAGE5n  = 5
	PAGE6n  = 6
	PAGE7n  = 7
	PAGE8n  = 8
	PAGE9n  = 9
	PAGE10n = 10
	PAGE11n = 11
	PAGE12n = 12
	PAGE13n = 13
	PAGE14n = 14
	PAGE15n = 15
)

const (
	EXTI0    EXTICR = 0x0F << 0  //+ EXTI 0 configuration.
	EXTI1    EXTICR = 0x0F << 4  //+ EXTI 1 configuration.
	EXTI2    EXTICR = 0x0F << 8  //+ EXTI 2 configuration.
	EXTI3    EXTICR = 0x0F << 12 //+ EXTI 3 configuration.
	EXTI0_PA EXTICR = 0x00 << 12 //  PA[0] pin.
	EXTI0_PB EXTICR = 0x01 << 0  //  PB[0] pin.
	EXTI0_PC EXTICR = 0x02 << 0  //  PC[0] pin.
	EXTI0_PD EXTICR = 0x03 << 0  //  PD[0] pin.
	EXTI0_PE EXTICR = 0x04 << 0  //  PE[0] pin.
	EXTI0_PF EXTICR = 0x05 << 0  //  PF[0] pin.
	EXTI0_PG EXTICR = 0x06 << 0  //  PG[0] pin.
	EXTI0_PH EXTICR = 0x07 << 0  //  PH[0] pin.
	EXTI1_PA EXTICR = 0x00 << 12 //  PA[1] pin.
	EXTI1_PB EXTICR = 0x01 << 4  //  PB[1] pin.
	EXTI1_PC EXTICR = 0x02 << 4  //  PC[1] pin.
	EXTI1_PD EXTICR = 0x03 << 4  //  PD[1] pin.
	EXTI1_PE EXTICR = 0x04 << 4  //  PE[1] pin.
	EXTI1_PF EXTICR = 0x05 << 4  //  PF[1] pin.
	EXTI1_PG EXTICR = 0x06 << 4  //  PG[1] pin.
	EXTI1_PH EXTICR = 0x07 << 4  //  PH[1] pin.
	EXTI2_PA EXTICR = 0x00 << 12 //  PA[2] pin.
	EXTI2_PB EXTICR = 0x01 << 8  //  PB[2] pin.
	EXTI2_PC EXTICR = 0x02 << 8  //  PC[2] pin.
	EXTI2_PD EXTICR = 0x03 << 8  //  PD[2] pin.
	EXTI2_PE EXTICR = 0x04 << 8  //  PE[2] pin.
	EXTI2_PF EXTICR = 0x05 << 8  //  PF[2] pin.
	EXTI2_PG EXTICR = 0x06 << 8  //  PG[2] pin.
	EXTI3_PA EXTICR = 0x00 << 12 //  PA[3] pin.
	EXTI3_PB EXTICR = 0x01 << 12 //  PB[3] pin.
	EXTI3_PC EXTICR = 0x02 << 12 //  PC[3] pin.
	EXTI3_PD EXTICR = 0x03 << 12 //  PD[3] pin.
	EXTI3_PE EXTICR = 0x04 << 12 //  PE[3] pin.
	EXTI3_PF EXTICR = 0x05 << 12 //  PE[3] pin.
	EXTI3_PG EXTICR = 0x06 << 12 //  PG[3] pin.
)

const (
	EXTI0n = 0
	EXTI1n = 4
	EXTI2n = 8
	EXTI3n = 12
)

const (
	LOCKUP_LOCK      CFGR2 = 0x01 << 0 //+ Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx.
	SRAM_PARITY_LOCK CFGR2 = 0x01 << 1 //+ Enables and locks the SRAM_PARITY error signal with Break Input of TIMx.
	PVD_LOCK         CFGR2 = 0x01 << 2 //+ Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register.
	BYP_ADDR_PAR     CFGR2 = 0x01 << 4 //+ Disables the adddress parity check on RAM.
	SRAM_PE          CFGR2 = 0x01 << 8 //+ SRAM Parity error flag.
)

const (
	LOCKUP_LOCKn      = 0
	SRAM_PARITY_LOCKn = 1
	PVD_LOCKn         = 2
	BYP_ADDR_PARn     = 4
	SRAM_PEn          = 8
)

const (
	ADC12_EXT2_RMP   CFGR4 = 0x01 << 0  //+ ADC12 regular channel EXT2 remap.
	ADC12_EXT3_RMP   CFGR4 = 0x01 << 1  //+ ADC12 regular channel EXT3 remap.
	ADC12_EXT5_RMP   CFGR4 = 0x01 << 2  //+ ADC12 regular channel EXT5 remap.
	ADC12_EXT13_RMP  CFGR4 = 0x01 << 3  //+ ADC12 regular channel EXT13 remap.
	ADC12_EXT15_RMP  CFGR4 = 0x01 << 4  //+ ADC12 regular channel EXT15 remap.
	ADC12_JEXT3_RMP  CFGR4 = 0x01 << 5  //+ ADC12 injected channel JEXT3 remap.
	ADC12_JEXT6_RMP  CFGR4 = 0x01 << 6  //+ ADC12 injected channel JEXT6 remap.
	ADC12_JEXT13_RMP CFGR4 = 0x01 << 7  //+ ADC12 injected channel JEXT13 remap.
	ADC34_EXT5_RMP   CFGR4 = 0x01 << 8  //+ ADC34 regular channel EXT5 remap.
	ADC34_EXT6_RMP   CFGR4 = 0x01 << 9  //+ ADC34 regular channel EXT6 remap.
	ADC34_EXT15_RMP  CFGR4 = 0x01 << 10 //+ ADC34 regular channel EXT15 remap.
	ADC34_JEXT5_RMP  CFGR4 = 0x01 << 11 //+ ADC34 injected channel JEXT5 remap.
	ADC34_JEXT11_RMP CFGR4 = 0x01 << 12 //+ ADC34 injected channel JEXT11 remap.
	ADC34_JEXT14_RMP CFGR4 = 0x01 << 13 //+ ADC34 injected channel JEXT14 remap.
)

const (
	ADC12_EXT2_RMPn   = 0
	ADC12_EXT3_RMPn   = 1
	ADC12_EXT5_RMPn   = 2
	ADC12_EXT13_RMPn  = 3
	ADC12_EXT15_RMPn  = 4
	ADC12_JEXT3_RMPn  = 5
	ADC12_JEXT6_RMPn  = 6
	ADC12_JEXT13_RMPn = 7
	ADC34_EXT5_RMPn   = 8
	ADC34_EXT6_RMPn   = 9
	ADC34_EXT15_RMPn  = 10
	ADC34_JEXT5_RMPn  = 11
	ADC34_JEXT11_RMPn = 12
	ADC34_JEXT14_RMPn = 13
)
